1. Field of the Invention
The present invention relates generally to a multi-chip package with ball grid array (BGA), and more particularly, to a multi-chip BGA package with improved rerouting configuration for better signal propagation and decoupling capacitors for reduced switching noise.
2. Description of the Related Art
Multi-chip packaging involves mounting two or more chips on a lead frame or a circuit board. specifically, a BGA multi-chip package employs conductive balls arranged to provide electrical connections with external electronics.
FIG. 1 shows an exemplary conventional multi-chip BGA package. Referring to FIG. 1, the multi-chip BGA package M1 includes lower and upper rerouted chips 10 and 20, interconnection bumps 5, a substrate 1, conductive balls 2, bonding wires 3, and an encapsulant 4.
The lower and upper rerouted chips 10 and 20 are spaced apart with active surfaces facing each other. Each rerouted chip 10 and 20 has a semiconductor chip 11 and 21, a first insulating layer 13 and 23, rerouting lines 14 and 24, and a second insulating layer 17 and 27.
Each semiconductor chip 11 and 21 is a center pad type. That is, chip pads 12 and 22 are arranged in a row along central lines on the active surface of each chip 11 and 21. The chip pads 12 and 22 protrude through a passivation layer (not shown) covering the active surface and made chiefly of silicon nitride.
The first insulating layer 13 and 23 of each rerouted chip 10 and 20 is on a passivation layer, exposing chip pads 12 and 22. The rerouting lines 14 and 24, also called redistribution lines, are formed on the first insulating layer 13 and 23 and electrically connect with respective chip pads 12 and 22. The rerouting lines 14 and 24 extend perpendicular to a row of the chip pads 12 and 22 and alternately reach opposing edges of the chip. The second insulating layer 17 and 27 covers both the first insulating layer 13 and 23 and the rerouting lines 14 and 24, exposing bump pads 15 and 25 which are integrated in the rerouting lines 14 and 24. The second insulating layer 17 of the lower chip 10 exposes bond pads 16.
Each interconnection bump 5 resides between corresponding lower and upper bump pads 15 and 25 and electrically connects the corresponding lower and upper rerouting lines 14 and 24.
The top surface of substrate 1 attaches to the back surface of lower chip 10 by adhesion. Conductive balls 2 arrange across the bottom surface of substrate 1 and electrically connect the package M1 to external electronics.
Bonding wires 3 electrically connect bond pads 16 of lower chip 10 to substrate 1. The encapsulant 4 provides the top surface of substrate 1 and covers the chips 10 and 20 and bonding wires 3.
The above-described conventional multi-chip BGA package 1 has drawbacks. For example, an increase in switching speed of the rerouted chip causes simultaneous switching noise due to fluctuation in chip power voltage. This often decreases chip speed, increases noise-like fluctuation and time distortion, as well as increasing other operation errors. Furthermore, when connecting a cable shield to a ground line, common-mode radiation occurs and serious electromagnetic interference (EMI) follows. Additionally, complicated interconnection schemes in conventional multi-chip BGA packages increase parasitic inductance and deteriorate electric signal propagation.